Abstract
Evaluating the time and voltage margin (vtMargin) of a wireline link across all possible corner cases is deemed unfeasible using time-domain methods. Statistical methods provide estimates at a fraction of time, at the potential cost of accuracy and neglecting the nonlinear behaviors of various link elements. We present a methodology to calculate the vtMargin of memory and serial links in a time-efficient manner while considering nonlinear behaviors of active blocks. Using a small initial dataset, regression analysis is performed to find multi-variable multi-order equations, which are then exhaustively evaluated across all possible combinations of corner cases to find a more comprehensive histogram representing the margin spread in the link.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.