Voids in silicon as sink for interstitials

Abstract

Transmission electron microscopy has been extensively used to quantify the reduction of extended defects formation in B- (up to 2 × 10 15/cm 2 at 80 keV) implanted regions of silicon crystals annealed at high temperatures. The suppression of dislocation formation does not depend on the depth at which voids are located, on their density and on the purity of the adopted silicon wafer. The carrier mobility measured in samples containing void layers is ideal, confirming that the presence of voids inhibits defect formation while they do not influence carrier mobility. Also B diffusivity, which is proportional to the interstitials concentration, is decreased when a void layer is present. The effects were observed for thermal treatments at temperatures higher than 1000°C. The results are interpreted on the basis of the measured efficiency of voids for the capture of interstitial silicon atoms.