VLSI-Implementation of Associative Memory Systems for Neural Information Processing

Abstract

Neural Networks and related associative networks or memories have raised a flurry of interest and research activities during the last decades. Currently technology has matured and neural networks and associative memories are employed more and more for demanding applications with real time requirements, e.g., control and automated visual quality inspection. Many neural structures are not easily amenable to formal analysis and efficient VLSI-implementation is hard to accomplish. In contrast, associative memories are more amenable to analysis and permit simple implementation as well as the development of modular architectures that scale up processing power with network size, while providing an easy to implement and inexpensive structure. System implementation providing interfaces and processing structure that allow embedding in a real-time signal processing environment gives access to massive parallelism and learning capability of these structures for real time applications. Waldschmidt (1987) gave a categorization of associative processors and architectures. He classifies an associative processor (ASP) as a SIMD (Single Instruction Multiple Data) consisting in the general case of two units, control unit and associative memory unit. Basically, four different forms of APS architecures can be distinguished: fully parallel ASP, bit-serial ASP, word-serial ASP, and block oriented ASP. The associative memory unit can be realised as a content addressable memory or as a standard RAM in conjunction with an association unit.