VLSI interconnect issues in definitive and stochastic environments

Abstract

A system designer needs to estimate the behavior of a system interconnection based on different patterns of switching which happen around an interconnect. Two different scenarios are supposed to estimate the effect of interconnect issues on system performance. First, based on a normalization technique for decreasing the number of a transfer function variables, a definitive environment for one interconnect is considered and an optimized look-up-table for the wire time delay is generated. Using some sampling methods, fast accessible look-up-tables are proposed for CAD tools in very simple and small one. A 4×4×4 table for the wire delay is introduced which results in very fast estimation. The average and maximum error of this look-up-table is less than 1% and 7.7% respectively, compared to HSPICE results. Second, the statistical environment of a wire in a BUS configuration is studied for all possible different switching patterns happening for the wires. Estimating the BUS main problems, including power consumption, crosstalk, and propagation delay for a random environment, which a wire senses in wide BUS, is only possible with statistical parameters like mean and variance. All simulations are done considering both wire inductive and capacitive couplings in HSPICE. Also, the secondary effect of crosstalk on propagation delay and power consumption is considered. The simulation results show 3.81% of BUS input switching can lead to a wrong decision on its wire load due to the crosstalk induced voltages in 90nm technology. The average induced crosstalk aware power consumption is 94μW. Also, the average of maximum crosstalk on the load can be as high as 25% of the Vdd.