VLSI implementation of a systolic database machine for relational algebra and hashing

Abstract

Database machines (DBMs) are motivated by the need for high speed query processing. Systolic arrays provide a promising future implementation for DBMs. A systolic architecture for a DBM capable of performing relational algebra operations is introduced in this paper. The array also supports the basic operations for hashing: member, insert and delete, in constant time. A VLSI implementation using a 3υ CMOS technology is analyzed. The systolic array is simple because it employs only one basic cell type. Using only one cell type reduces design time and cost and enhances reliability of DBMs.