VLSI implementation of a scalable K-best MIMO detector

Abstract

Multiple-input multiple-output (MIMO) communication systems enable high data rates to be achieved compared to single-antenna systems, however, they also incur a huge complexity cost to the receiver. For tree search MIMO detection techniques such as the K-best algorithm, the critical path length of the detector is also found to scale linearly with the number of antennas, which limits the maximum clock frequency that can be achieved especially at larger MIMO dimensions. In this paper, we present a novel K-best detector that incurs a fixed critical path length irrespective of the number of antennas. This is achieved by incrementally computing the interference terms of previously detected symbols rather than computing them at once like in the conventional K-best detector. Synthesis results show that the optimized detector achieves approximately a 2× maximum clock frequency improvement compared with the conventional K-best implementation. We also present an approximate sorting algorithm that determines the K-best candidates in a distributed fashion, which allows a low complexity to be achieved. The proposed K-best detector is implemented for a 4 × 4 64-QAM MIMO system using a folded architecture and a single core is able to achieve a throughput of 300 Mbps and an energy efficiency of 76.9 pJ/bit, which compares favourably with other folded architectures in the literature.