Abstract
The purpose of the programmable DSP chip is to provide a prototype of the processor that will be a part of the multi-processor multi-chip 3-D OESP demonstrator system. This chip design extends upon the DSP core above to provide more flexibility and functionality. The architecture for this chip is motivated by the desire to match the processor performance to the access time of the static RAM included with the processor. To achieve this, the separable nature of algorithms such as FFT and DCT was exploited. Multiple parts of the problem can be stored in separate RAMs and threaded through the processor so as to allow the RAM appropriate recovery time between accesses.
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