Vlsi Design of Cache Compression in Microprocessor Using Pattern Matching Technique

Abstract

Microprocessors speeds have been increasing faster than speed of off-chip memory. When multi processors are used in the system design, more processors require more accesses to memory. Thus it raises a 'wall' between processor and memory. Accessing off-chip memory takes an order of magnitude more time than accessing an on-chip cache, two orders of magnitude more time than executing an instruction. Cache compression presents the challenge that the processor speed has to be improved but it should not substantially increase the total chip's power consumption. This Cellular Automata (CA) based pattern matching architecture has number of novel features tailored for the application. The compression is based on pattern matching and dictionary matching and if the pattern matches, the dictionary matching has to be bypassed. The compressor is composed of Pattern matching and Priority Unit. In this paper modified Priority unit is proposed. By this method the speed and the power can be improved without affecting the performance of system cache.