VLSI Design of a High Throughput Hybrid Precoding Processor for Wireless MIMO Systems

Abstract

Hybrid precoding, a combination of radio frequency (RF) beamforming and digital precoding, has been investigated intensively these days for millimeter wave (mmWave) communication systems employing large antenna arrays. The key problem is constructing beamforming and precoding matrices for the RF beamformer and the digital baseband, respectively, based on the channel matrix decomposition result. This paper presents a new computing algorithm to achieve the matrix decomposition efficiently without compromising the performance. The algorithm computes beamforming (steering) and precoding matrices in separate phases to alleviate the computing overheads of iterative matrix updates. This measure also creates the computing parallelism to facilitate efficient hardware implementation. A novel computing scheme based on QR decomposition and blockwise inversion techniques is also developed to tackle the most critical least square solution module. This leads to a computing complexity reduction by a factor of $0.3~{N}$ when compared with the popular orthogonal matching pursuit (OMP) scheme, where ${N}$ is the antenna array size. The simulation results indicate the percentage of choosing correct steering vectors is 90%, which is as good as the OMP scheme can achieve. A hardware accelerator design of the proposed scheme is developed by using a TSMC 40 nm CLN40G technology. The design, with a gate count of 419.3 k, can operate up to 333 MHz with a power consumption of 267.1 mW. This suggests a throughput rate of processing 10.4 M channel matrices per second. The core size is merely 0.58 mm2 while the entire die size including I/O pads is 2.26 mm2 .