VLSI Design and Investigation of an Area Efficient and Low Power MOD-R2MDC FFT for MOMO-OFDM

Abstract

In this paper, an area-efficient low power fast Fourier transform processor is proposed for multi input multi output-orthogonal frequency division multiplexing (MIMO-OFDM) in wireless communication system. It consists of a modified architecture of radix-2 (R2) algorithm which is described as modified R2 multipath delay commutation (MOD-R2MDC). OFDM is a popular method for high data rate wireless transmission. This paper describes the very large scale integration design of an area efficient MOD-R2MDC FFT for MIMO-OFDM system targeted to future wireless communication systems. The very high speed integrated hardware description language simulation results have been tested practically by implementing in the Altera development and education-2 field programmed gate array (FPGA) development board. Also the existing OFDM system has been tested with these FFT algorithms and their performances were analyzed with respect to occupation of area in FPGA and power consumption. A low-power and area efficient architecture enables the real-time operations of MIMO-OFDM system.