VLSI considerations for TESH: a new hierarchical interconnection network for 3-D integration

Abstract

This paper discusses very large scale integration (VLSI) issues, including reconfiguration and yield, for a new interconnection network, Tori connected mESHes (TESH). Its key features are the following: (1) it is hierarchical, thus allowing exploitation of computation locality as well as easy expansion up to a million processors, (2) it permits efficient VLSI/ULSI (ultralarge scale integration) realization, and (3) it appears to be well suited for three-dimensional (3-D) implementation. This is due in part to the fact that it requires far fewer number of vertical wires than most other multicomputer networks of comparable diameter, as demonstrated by a 4096 node example. Presented in the paper are the architecture of the new network, node addressing and message routing, VLSI considerations, and most importantly, the reconfiguration and yield studies.