VLSI Circuit Partitioning Using Ant Colony Optimisation to Yield Fault Tolerant Testable Systems

Abstract

As CMOS technology enters the nanometer regime, digital designs are becoming more susceptible to permanent, transient and delay faults. Due to higher probability of faults, there is a fundamental need for addressing reliability and design for testability (DFT) issues, while designing fault tolerant VLSI systems. In this paper, a simulation framework and optimisation technique are presented to guide partitioning of VLSI circuits in order to develop fault tolerant testable designs. This framework utilises ant colony optimisation (ACO) and a primary input primary output fan in fan out partitioning algorithm to determine the optimal DFT locations. The DFT cells are added at the partition points to apply pseudo-exhaustive test patterns for fault detection. The number of DFT cells to be inserted and its locations are critical as it affects the system reliability and performance. Hence, their selection is crucial in order to optimise system performance and reliability. In the present work, the design constraints of the partitioned circuit considered for optimisation include critical path delay, hardware overhead, reliability and test time. ACO uses the parameters of the circuit obtained after partitioning, to determine the optimal values of circuits maximum primary input cone size (N) and minimum fan-out value (F) to decide on the number of partitions and its locations. Experiments conducted using ISCAS85 benchmark circuits demonstrate that this novel approach significantly outperforms results of the state-of-the-art works. The effectiveness of proposed optimisation technique is verified using hardware implementation of the partitioned system in Virtex-6E field programmable gate array.