Abstract
An alternative design of VLSI-based array dividers with concurrent error detection by recomputing using partitioned architecture (REPA) is proposed. The basic concept is that the divider array can be divided into two identical parts and its operation can be completed by using one part through two iterative calculations. With two such parts, a concurrent error detection scheme can be designed by using a space redundancy approach, and the detecting action is achieved at each iteration. The design is better than previous designs, such as RESO and AL, in terms of area requirement, time penalty, fault model and error latency. Advanced analysis of m partitions is also included. The experimental results are attractive, especially for designs with application-specified trade-offs between speed performance and area cost.
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