VLSI Based Architecture in ECG Monitoring for Adaptive Power Management In Wireless Bio Signal Acquisition Network

Abstract

For the diagnosis and elimination of cardiovascular diseases, the ECG system has evolved as smarter healthcare professionals. As almost all of these networks are battery-operated, the whole device’s total life is greatly shortened by self-centred communication connections. This paper will present a power control technique and the accompanying VLSI design to improve the Asic ECG heart monitor’s lifespan powered by the battery. The suggested power control strategy dynamically adjusts between two transmission modes, i.e. high performance / lower energy modes, available for a device’s energy level. Because localized storage is energy, for true monitoring of QRS complexity and breathing rates assessment, a streamlined methodology focusing on slopes improvement with runtime adaptive thresholding is intended to guarantee maximum energy usage throughout limited energy level. The required communication mode is chosen based mostly on batteries and pulse rate consistency, which essentially fulfils the Wireless Body Sensor Communication network objective. Collecting appropriate ECG collections from a single customer and enhancing the longevity of the device. Response and efficiency are evaluated for the proposed method The ultra - low - power signal generator with a relaxing scope range of 1-3 m will be built to retain a bigger battery. Any transmitter and receiver for remote private communication standards have been established lately. It is not the best option for ultra-low power WBAN implementations. The Spartan 6 FPGA design has been introduced with a peak clock frequency of 269 MHz with an energy demand of 0.3mW, specially designed for actual ECG measurement techniques.