Abstract
VLSI architectures of filterbanks necessary for an HDTV subband codec have been investigated. Different techniques have been combined in order to achieve a compact realization. The application of special QMF structures results in a further reduction of hardware expense. High clocking rates are handled using two dimensional polyphase filterbanks in combination with pipelining and parallel processing. An architecture suitable for one-chip implementation of a 10 x 14 tap QM filterbank has been developed.
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