Abstract
The paper presents an overview on architectures for VLSI implementations of video compression schemes as specified by standardization committees of the ITU and ISO, focussing on programmable architectures. Programmable video signal processors are classified and specified as homogeneous and heterogeneous processor architectures. Heterogeneous processors outperform homogeneous processors due to adaptation to the requirements of special subtasks by dedicated modules. The majority of heterogeneous processors incorporate dedicated modules for high performance subtasks of high regularity like DCT and block matching. By normalization to a fictive 1.0 micron CMOS process typical linear relationships between silicon area and throughput rate have been determined for the different architectural styles. This relationship indicates a figure of merit for silicon efficiency.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
