Abstract
The VLSI implementation of SISO‐MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space‐time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add‐compare‐select‐offset (ACSO) unit, A‐, B‐, Γ‐, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding‐window‐technique‐based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.
Highlights
The ability of turbo codes (TCs) to achieve very low BER that approaches the Shannon limit is very attractive
The VLSI architectures of space-time turbo trellis coding decoders as well as of a set of soft-in soft-out (SISO)-maximum a posteriori (MAP) component channel decoders used in turbo coding are proposed and investigated
The space-time turbo code receiver as opposed to binary turbo codes is based on nonbinary trellises, which imposes a number of differences
Summary
The ability of turbo codes (TCs) to achieve very low BER that approaches the Shannon limit is very attractive. The principles of iterative turbo decoding can be combined with those of space-time coding resulting in a bandwidth efficient low-error-rate channel coding scheme named space-time turbo trellis coding (STTuTC) [6,7,8,9,10]. The latter scheme benefits from the impressive coding gain of turbo codes and the diversity gain of space-time codes, to obtain a very power-efficient system. The sliding window technique (SWT) presented in [17,18,19,20,21] enables the early acquisition of the state metric values without having to scan the whole trellis frame in the one direction before scanning the other, and this results in reduced elementary decoder latency as well as smaller state metric memory requirements
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