VLSI and AES based IoT security by Modified Random S- Box Generation

Abstract

The next phase of the digital revolution is the Internet of Things (IoT), which refers to the scenario in which billions of people and objects are interconnected to permit the flow of enormous volumes of information from many locations. This development is due to the extraordinary expansion in Integrated circuit and sensor technology. IoT’s data transit phases have some security issues with data confidentiality. Along with some benefits and its high usage, some complexity issues arise in form of numerous forms. Thus, a security system is suggested in this research paper that tackles the aforementioned difficulties in order to improve reliable information transmission in a smart IoT scenario with low power consumption, throughout information sending among an IoT system and a cloud server using revised Advance Encryption Standard with random S- Box which is generated by various (nine) irreducible polynomial GF (2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> ) in finite field techniques. In the revised S- Box generation, this research aims to optimize the VLSI circuit design of the SubBytes and inverse SubBytes procedures. To achieve this, all of the building blocks in the modified random S-box transformation are done by finite field arithmetic. For further improvement of the area performance, a blended design of modified S-boxes and inverse S-boxes is suggested where on each occasion a different irreducible polynomial is utilized in the finite field of GF (2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> ) and this irreducible polynomial and secret key is sent to the receiver. As a result, a random S-Box is formed and thereby the algorithm's security is improved.