Abstract
A 1.0 μM CMOS technology with 3 layers of metal is used to implement a high density Master Image that contains LOGIC and RAMs. The Image allows the usage of more than 1,000,000 transistors. A hierarchical design methodology is applied. This chip offers variable sized physical partitions and RAM macros. No fixed area sizes and locations for partitions and macros are necessary. Density and performance of custom chips are approached by the described methodology with significantly lower development cost and time.
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