Visualization of 0.1-μm-metal-oxide-semiconductor field-effect transistors by cross-sectional scanning tunneling microscopy

Abstract

The device structure of 0.1-μm-metal-oxide-semiconductor field-effect transistors (MOSFETs) has been examined by cross-sectional scanning tunneling microscopy (STM). Topographic STM images display the source/drain, gate, channel, gate oxide, and spacer of the MOSFETs in terms of height, where these regions appear as though they are a different height from each other. The bias voltage dependence of the STM images shows that the contrast observed by STM reflects the differences in carrier densities between the regions in addition to that in the corrugations. The dimensions of these regions as obtained from the images are consistent with the specifications of devices in feature size that we fabricated.