Viser: providing serializability in hardware with simplified cache coherence

Abstract

While existing architectures like x86 and SPARC provide strong hardware memory consistency models, such as TSO, programming language memory models are more relaxed. This divide nullifies the usefulness of providing strong hardware memory models, since languages and compilers provide a weaker guarantee. Moreover, current shared memory systems implement complex cache coherence protocols which add to the complexity. This work proposes a microarchitecture, called Viser, that ensures strong semantics---serializability of synchronization-free regions (SFRs)---in the absence of region conflicts even for racy program executions. Given an execution, Viser either reports a serializability violation or guarantees SFR-serializability, in effect providing the same guarantees provided by languages such as C++ and Java for data-race-free programs only. Viser's design also allows for greatly simplifying existing cache coherence protocols, without requiring any assumptions about language-level properties such as data-race-freedom.