Virtual Impedance Loop for Droop-Controlled Single-Phase Parallel Inverters Using a Second-Order General-Integrator Scheme

Abstract

This paper explores the impact of the output impedance on the active and reactive power flows between parallelized inverters operating with the droop method. In these systems, a virtual output impedance is usually added to the control loop of each inverter to improve the reactive power sharing, regardless of line-impedance unbalances and the sharing of nonlinear loads. The virtual impedance is usually implemented as the time derivative of the inverter output current, which makes the system highly sensitive to the output current noise and to nonlinear loads with high slew rate. To solve this, a second-order general-integrator (SOGI) scheme is proposed to implement the virtual impedance, which is less sensitive to the output current noise, avoids to perform the time derivative function, achieves better output-voltage total harmonic distortion, and enhances the sharing of nonlinear loads. Experimental results with two 2-kVA inverter systems under linear and nonlinear loads are provided to validate this approach.