Abstract
Network on Chip (NoC) connects multiple cores on a single chip. Traditionally input queued routers were used to arrange packets in a fixed order in a Virtual Channel (VC). This leads to Head of Line (HoL) blocking and increased latency. To address this issue, a VC router architecture is proposed which minimizes the total number of pipeline stages and uses a special buffer to avoid HoL blocking. The design is implemented using Booksim and the results show improved latency over conventional router.
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