Virtual Armature Resistance-Based Control for Fault Current Limiting in a High-Order VSG and the Impact on Its Transient Stability

Abstract

This article proposes a fault ride through (FRT) technique for a high-order virtual synchronous generator (VSG) that adjusts its virtual armature resistance. When a fault is detected by a dedicated algorithm, the proposed control adjusts the resistance parameter accordingly. The main contribution of this article is to adjust the virtual resistance directly in the machine model to limit the current during faults, unlike other techniques proposed in the literature that add another control loop to produce the virtual impedance effects. To validate the effectiveness of the proposed control, a hardware-in-the-loop real-time simulation platform was adopted using a Typhoon HIL 402 device and a Texas Instruments F28379D digital controller. The results demonstrate that the control effectively limits the converter’s current while still contributing to raising the system’s critical clearing time (CCT) and improving transient stability. The proposed FRT strategy is validated in a three-phase fault scenario in which a 500 kVA–480 V converter’s peak fault current is reduced from 5 kA to 1.4 kA, depending on the resistance value adjusted. The transient stability is also analyzed in 30 different scenarios and the VSG support on the CCT is reduced by 23 ms on average. However, when compared to the baseline scenario without the VSG, the system still sees an increase in CCT with the current limiting control applied. Additionally, the control allows the VSG to smoothly transition to island mode in a scenario where the fault is cleared and the grid is disconnected by a protection system.