Virtex 7 FPGA Implementation of 256 Bit Key AES Algorithm with Key Schedule and Sub Bytes Block Optimization

Abstract

Hardware Security plays a major role in most of the applications which include net banking, e-commerce, military, satellite, wireless communications, electronic gadgets, digital image processing, etc. Cryptography is associated with the process of converting ordinary plain text into unintelligible text and vice versa. There are three types of cryptographic techniques; Symmetric key cryptography, Hash functions and Public key cryptography. Symmetric key algorithms namely Advanced Encryption Standard (AES), and Data Encryption Standard use the same key for encryption and decryption. It is much faster, easy to implement and requires less processing power. The proposed 256-bit AES algorithm is highly optimized in Key schedule and Sub bytes blocks, for Area and Power. The optimization has been done by reusing the S-box block. We are optimizing the algorithm with a new approach where internal operations are 32-bit operations, as compared to 128-bit operations. The proposed implementation helps in re-using the same hardware in a pipelined fashion which results in an area reduction by 72% using slice registers, 62% using slice LUT's and 61% using LUT-FF Pairs. This in turn results in a power reduction by 78% in a FPGA implementation. The throughput (Mbps) of the proposed implementation using Virtex-7 (xc7vx485tffg1157) FPGA improved by 10%.