Video Compression Based on FPGA Using SIMD Architecture

Hayder Waleed Shnain ,Mohammed Najm Abdullah ,Hassan Awheed Jeiad

doi:10.33103/uot.ijccce.21.1.6

Hayder Waleed Shnain , Mohammed Najm Abdullah + Show 1 more

Open Access

https://doi.org/10.33103/uot.ijccce.21.1.6

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Abstract

Recently, video files and images have became the dominant media material for transmitting or storing across different applications that are used by different people. So, there was a serious need to find more effective and efficient video compression techniques to reduce the large size of such multimedia files. This paper proposes SIMD based FPGA lossless JPEG video compression system with the facility of scalability. Generally, the proposed system consists of a software side and a hardware side. The digital video file is prepared to be processed by the hardware side frame by frame on the software side. The hardware side is proposed to consist of two main processing circuits, which are the prediction circuit for calculating the predicted value of each pixel in the certain frame and the encoding circuit that was represented by a modified RLE (Run-Length-Encoder) to encode the result obtained through subtracting the predicted value from the real value for each pixel to produce the final compressed video file. The compression ratio obtained for the proposed system is equal to 1.7493. The throughput improvement for the two and four processing units basing on SIMD architecture was 100 MP/s and 200 MP/s, respectively. The clock results showed that the number of clocks required had become 50% and 25% when using two processing units and four processing units, respectively, from the number of clocks using single processing units. Index Terms— Video Compression, Lossless JPEG, RLE, FPGA.

Highlights

The embedded system tends to be more complex and combine multiple functions in one system
Silva et al [11], the authors offered video compression with scalability by using single instruction multiple data (SIMD) architectures based on FPGA where using low complexity lossless compression for images (LOCO-I) algorithm
The connection between the laptop and FPGA board is done by using Universal Serial Bus (USB) cable

Summary

INTRODUCTION

The embedded system tends to be more complex and combine multiple functions in one system. The need for robust architecture increased with high executive performance, and a chip with multiple cores became very common, and especially single instruction multiple data (SIMD) It applies the same set of instructions to various data elements. Inatsuki et al [10] the authors suggested real-time lossless and near-lossless video compression and implement it by using JPEG-Ls and DPCM algorithm and using Huffman coding as an entropy encoder; and this system achieves a compression ratio of 1.818, and the maximum data throughput is 148.5 Mpixles/s. Silva et al [11], the authors offered video compression with scalability by using SIMD architectures based on FPGA where using low complexity lossless compression for images (LOCO-I) algorithm.

THE PROPOSED SYSTEM

IMPLEMENTATION AND RESULTS

CONCLUSIONS