Via Processing Effects on Electromigration in 65 nm Technology

Abstract

We investigate the key factors controlling electromigration (EM) in 65 nm technology node. For UP EM (EM for up-directional electron flow at the cathode via), via barrier coverage strongly affects EM reliability for dual-damascene (DD) interconnects. A critical dimension of upper metal patterns caused a shadow effect for the PVD barrier process, which resulted in non-conformal barrier deposition inside the via and a significant degradation in UP EM reliability. The UP EM reliability has been improved with the enhanced barrier coverage inside via and optimized for performance with the reduced overall barrier deposition. For DN EM (EM for down-directional electron flow at the cathode), the via bottom interface turns out to be a key factor controlling EM reliability. The early DN EM failures, in which thin void growth along the via bottom interface fails the interconnect in a short time frame, can be due to poor process controls (i.e., excessive via clean) resulting in a fast diffusion path at the interface. In 65 nm node, UP and DN EM have different via processing effects and need optimization for reliability enhancement