Via Bottom Profile Optimization in All-in-One Etch with Double Patterning Scheme

Abstract

In advanced CMOS technology node with Cu/low-K interconnection, double patterning scheme with Metal Hard-Mask (MHM) All-In-One (AIO) etch is used to define smaller via and trench. The bottom profile of via is critical for via connectivity and RC delay. Tapered via bottom profile means smaller contact area with lower metal which means larger via contact resistance and degradation of chip interconnect performance. The bottom profile of via might probably become tapered when it enters Etch Stop Layer (ESL) or when the plasma touches lower Cu layer. In this paper, we will explain the reason of tapered via bottom profile and several ways to solve this problem.