VHDL Implementation of Scheduled Dataflow Architecture and the Impact of Efficient Way of Passing of Data

Abstract

Since the invention of microprocessors around 1970, CPU performance improvement together with the Instruction Level Parallelism (ILP) had been the main focus of the computer industry. Recently, ILP seemed to have reached its limit and together with the problem of power consumption and heat dissipation, emerged the multi-core era. The focus had shifted from ILP to Thread Level Parallelism (TLP) and efficient use of multi-core processors. However, the detection of RAW hazard technique relies on complex hardware in the current computers, which may cause the designers to make the CPU consume lot of energy and the design to be more complex. By using dataflow paradigm, this can naturally eliminate the RAW hazards. This new architecture uses a paradigm, to closely link the ILP and TLP by combining the sequential and dataflow approach. It is designed using VHDL language and tested on Alter a DE2 board. With just two register sets, tremendous amount of performance improvement can be gained. This architecture not only reduces the latency of memory accesses, but also can be suitable for multithreaded multi-core platforms.