Abstract
The Very Large Scale Integration (VLSI) has a dramatic impact on the growth of digital technology. VLSI has not only reduced the size and the cost, but also increased the complexity of the circuits. Due increase there is a problem of circuit testing, which becomes increasingly difficult as the scale of integration grows. One solution to this problem is to add logic to the IC so that it can test itself. In this paper we have design GCD (greatest common divider) processors in VHDL with BIST capability and compared the area overhead of with and without BIST.
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