Abstract
In this paper we present a translation from high-level specifications written in the formal description technique LOTOS to hardware descriptions in the standard language VHDL. The objective is to use the formal foundation of LOTOS in order to improve the design phase of hardware components. VHDL is used as an intermediate step, taking advantage of the existing simulation and synthesis tools. The translation methodology proposed in this paper has required the extension of LOTOS with timing features and will be supported by automatic tools, that are already under development.
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