Abstract
A very low power consumption viterbi decoder has been developed by low supply voltage and 0.15 µm CMOS process technology. Significant power reduction can be achieved by modifying the design and implementation of viterbi decoder using conventional techniques traceback and Register Exchange to Hybrid Register Exchange Method (HREM), Minimum Transition Register Exchange Method (MTREM), Minimum Transition Hybrid Register Exchange Method (MTHREM), Register exchangeless Method and Hybrid Register exchangeless Method. By employing the above said schemes such as, HREM, MTREM, MTHREM, Register exchangeless Method and Hybrid Register exchangeless Method; the viterbi decoder achieves a drastic reduction in power consumption below 100 µW at a supply voltage of 1.62 V when the data rate of 5 Mb/s and the bit error rate is less than 10-3. This excellent performance has been paved the way to employing the strong forward error correction and low power consumption portable terminals for personnel communication, mobile multimedia communication and digital audio broadcasting. Implementation insight and general conclusions can particularly benefit from this approach are given.
Highlights
The convolutional encoding and viterbi decoding schemes [1] is used by many mobile communication, satellite communication or broadcasting systems [2, 3]
The goal of the approach proposed in this paper is to reduce power consumption while decoding convolutional codes in a system where acceptable bit error rate varies in real time
The exchangeless viterbi decoder is a low power design for the viterbi decoder with the restriction of resetting the encoder register after each ‘L’ encoded data bits and it can be used for a bit error rate of acceptable limit 10-5 to 0.03 for wireless applications with the assumption that there will be no consecutive errors
Summary
The convolutional encoding and viterbi decoding schemes [1] is used by many mobile communication, satellite communication or broadcasting systems [2, 3]. To counteract the exponential dependence of viterbi decoder complexity on memory order in low power designs, good power reduction methods are needed. As in the case of memory designs today, the significant power reduction potential lies in the dynamically varying a viterbi decoder implementation according to real time changes in system characteristics. The goal of the approach proposed in this paper is to reduce power consumption while decoding convolutional codes in a system where acceptable bit error rate varies in real time. 1) A system dependent, low power approach for decoding convolutional codes namely Hybrid Register Exchange Method (HREM), Minimum Transition Register Exchange Method (MTREM), Minimum Transition Hybrid Register Exchange Method (MTHREM), Register exchangeless Method and Hybrid Register exchangeless Methods are demonstrated. 2) Variation in the potential of these approaches as system characteristic maximum acceptable bit error rate (MABER) varies is studied. 3) Comparisons of power reduction potential of above mentioned approaches are demonstrated
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
