Very high speed differential optoelectronic algorithmic ADC using n–i(MQW)–n SEED technology

Abstract

This paper describes the design of a very high speed optoelectronic analog digital converter based on a digital division algorithm called SRT division using n–i(MQW)–n Self Electro-Optic Effect Device (SEED) technology. The proposed structure is a pipeline ADC. The SRT algorithm was chosen because it provides a redundancy at each stage of the pipeline. The amount of redundancy is dependent on the radix of the SRT algorithm and the number set chosen. The relation between the SRT radix, number set and the division full range is given in this paper. Also a macro-model for the n–i(MQW)–n device was developed and used to simulate all the circuitry and algorithmic operations needed for the ADC. These included analog addition, analog subtraction and integer multiplication. Based on the developed macro-model and n–i(MQW)–n SEED circuit modules a basic unit of the algorithmic ADC was designed.