Vertical WS2/SnS2 van der Waals Heterostructure for Tunneling Transistors

Jiaxin Wang,Haisheng Song,Cheng Chen,Ru Huang,Feng Miao,Chen Pan,Yuchao Yang,Jiadi Zhu,Qianqian Huang,Huimin Wang,Rundong Jia,Yawen Zhang

doi:10.1038/s41598-018-35661-4

Abstract

Van der Waals heterostructures composed of two-dimensional (2D) transition metal dichalcogenides (TMD) materials have stimulated tremendous research interest in various device applications, especially in energy-efficient future-generation electronics. Such ultra-thin stacks as tunnel junction theoretically present unprecedented possibilities of tunable relative band alignment and pristine interfaces, which enable significant performance enhancement for steep-slope tunneling transistors. In this work, the optimal 2D-2D heterostructure for tunneling transistors is presented and elaborately engineered, taking into consideration both electric properties and material stability. The key challenges, including band alignment and metal-to-2D semiconductor contact resistances, are optimized separately for integration. By using a new dry transfer technique for the vertical stack, the selected WS2/SnS2 heterostructure-based tunneling transistor is fabricated for the first time, and exhibits superior performance with comparable on-state current and steeper subthreshold slope than conventional FET, as well as on-off current ratio over 106 which is among the highest value of 2D-2D tunneling transistors. A visible negative differential resistance feature is also observed. This work shows the great potential of 2D layered semiconductors for new heterostructure devices and can guide possible development of energy-efficient future-generation electronics.

Highlights

Thin two-dimensional (2D) semiconductors beyond graphene have emerged as one of the most promising material candidate for generation electronic devices because of their sizable bandgap[1,2,3,4,5,6]
Tunneling transistors based on van der Waals heterostructures are expected to realize low leakage current, ultra-steep slope and high on/off current ratio simultaneously, which has been confirmed by lots of theoretical works and shows the great potential in low power electronics[9,10,11,12]
The channel layer is designed to be under the source layer, and the electric potential and carrier concentration of the channel layer are modulated by the bottom gate

Summary

Introduction

Thin two-dimensional (2D) semiconductors beyond graphene have emerged as one of the most promising material candidate for generation electronic devices because of their sizable bandgap[1,2,3,4,5,6]. Tunneling transistors based on van der Waals heterostructures are expected to realize low leakage current, ultra-steep slope and high on/off current ratio simultaneously, which has been confirmed by lots of theoretical works and shows the great potential in low power electronics[9,10,11,12]. The stable WS2/SnS2 van der Waals heterostructure with theoretically 0.02 eV Ebeff is considered for the first time and selected as the optimal material platform for tunneling transistors. This optimal heterostructure is further experimentally demonstrated, and the WS2 and SnS2 serve as the p-type source layer and the n-type channel and drain layer, respectively. This work shows the great potential of van der Waals heterostructure for tunneling devices and future-generation energy-efficient electronics

Methods

Results

Conclusion