Vertical silicon-on-nothing FET: Threshold voltage calculation using compact capacitance model

Abstract

The threshold voltage ( V th) model of the novel vertical fully-depleted silicon-on-nothing FET (VFD SONFET) structure is extracted from the compact capacitance equivalent circuit. Due to the absence of the transistor substrate in the VFD SONFET, the channel region is coupled to the source and drain through the buried oxide. Electrostatically, the VFD SONFET resembles the SOI device with thick buried oxide and recessed source/drain, and the developed model can also be applied to these structures. This property is modeled by two-dimensional buried oxide capacitance ( C BOX), which competes for the inversion charge with gate oxide capacitance ( C GOX). Therefore, the V th is primarily influenced by the ratio of buried and gate oxide capacitances, with the negligible effect of the silicon body equivalent capacitance and the silicon body charge. The relative impact of C BOX increases with the down-scaling of the effective channel length. In the VFD SONFET structure, the inversion channel can be formed at the back interface of the channel region, due to its coupling to the n + source and drain regions. However, it is shown by the model that the V th value is minimally changed in this case, due to a small potential change in the silicon channel. The model accurately predicts V th in comparison to physical simulations, especially in the long channel region, whereas accuracy drops for shorter channels. The maximum absolute deviation is below 50 mV for the channel lengths above 30 nm.