Vertical MOS transistor with threshold voltage adjustment

Abstract

A sub-half micron channel length vertical MOS transistor was successfully developed for processing with less expensive process equipment. One of the important advantages of vertical MOS transistor technology is that the channel length scaling is not limited by the minimum lithographic resolution. The vertical MOS transistor, by virtue of increased W and smaller L, allowed the utilization of the side-walls of a 3D trench to form the transistor channel. The device will have much higher drain current and operating frequency than a planar MOS transistor patterned in the same planar surface area. Conventional processes such as ion implantation cannot be used to control the threshold voltage (V/sub t/) of a vertical MOS transistor. A new method for diffusion of the impurities from a doped CVD film was successfully developed for vertical MOS transistor V/sub t/ adjustment.