Vertical GaN power FET on bulk GaN substrate

Abstract

Lateral GaN transistors on Si substrates operating at voltage below 650 V are commercially available today. The main drawback of this lateral geometry is that the transistor area (and, therefore, its cost) is proportional to the breakdown voltage. In addition, numerous material interfaces are exposed to high electric fields, which reduces reliability and prevents avalanche breakdown. For higher-voltage high-current applications, the lateral-device size increases dramatically, and very high current levels are difficult to handle on just one surface. It is expected that vertical devices would reduce the die size and be more reliable as the electric field peaks far away from the surface. The most studied vertical GaN transistor, the current aperture vertical electron transistor (CAVET), has made significant progress in performance, but it still faces two challenges [1]. First, the CAVET structure requires a p-doped current blocking layer buried in the n-doped GaN layer. Fully activating the p-dopant Mg in GaN has been found very challenging and the vertical leakage current tends to be high. Second, the needs for a high quality regrowth of the AlGaN/GaN access region substantially increases the manufacturing cost. In this work, a novel vertical FET (VFET) structure on bulk GaN substrate has been developed to address the challenges of conventional power vertical GaN transistors (Fig. 1). This VFET structure does not require a p-doped GaN current-blocking layer or material regrowth. A GaN VFET with 0.5 V threshold voltage and 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> on/off current ratio was demonstrated.