Abstract

A detector concept based on hybrid planar pixel-detector technology is under development for the CLIC vertex detector. It comprises fast, low-power and small-pitch readout ASICs implemented in 65 nm CMOS technology (CLICpix) coupled to ultra-thin sensors via low-mass interconnects. The power dissipation of the readout chips is reduced by means of power pulsing, allowing for a cooling system based on forced gas flow. In this paper the CLIC vertex-detector requirements are reviewed and the current status of R&D on sensors, readout and detector integration is presented.

Highlights

  • The CLIC project studies the feasibility of a linear electron-positron collider optimized for a centreof-mass energy of 3 TeV with an instantaneous luminosity of a few times 1034cm−2s−1, using a novel technique called two-beam acceleration [1]

  • The creation of the Beamstrahlung photons reduces the available centre-of-mass energy of the e+e− collisions and their interaction leads to lepton pairs and hadrons, most of which are produced at very low polar angles and are contained in the beam-pipe by the axial magnetic field [4]

  • The central beam-pipe walls have to be placed outside the high-rate region and the inner detectors have to be efficiently shielded from back-scattered particles originating from the forward region

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Summary

The CLIC machine environment

The CLIC project studies the feasibility of a linear electron-positron collider optimized for a centreof-mass energy of 3 TeV with an instantaneous luminosity of a few times 1034cm−2s−1, using a novel technique called two-beam acceleration [1]. In order to reach its design luminosity of 6 × 1034cm−2s−1 at a maximum centre-of-mass energy of 3 TeV, CLIC will operate with very small bunch sizes (σx × σy × σz ≈ 40nm × 1nm × 44μm). Accelerating structures of 12 GHz drive the two main beams and collisions occur in bunch crossings (BX) every 0.5 ns for a train duration of 156 ns. The power consumption of the detectors, and the material required for cooling infrastructure, can be reduced by switching off parts of the frontend electronics during the 20 ms gaps between trains

Beam-induced backgrounds
Vertex-detector requirements
Detector concepts
Hybrid readout technology
Thin-sensor assemblies
Simulation of signals in silicon
Detector integration
Findings
Conclusions
Full Text
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