Abstract
General-purpose many-core network processors have been widely used in network packet processing due to its high programmability and parallel processing ability. The design of general-purpose many-core network processors involves a lot of key technologies, including packet scheduling, inter-core communication, co-processing, etc. The verification of these technologies is essential before applied to the system. However, there are some of limitations in the current software-based verification platform, such as low simulation speed and fidelity. A FPGA-based verification platform for general-purpose manycore network processors (VeriNP) is proposed in this paper. The VeriNP supports verification of network processor for at least 16 real RISC CPU cores, and the frequent of cores can run at 100MHz or higher. Based on the VeriNP platform, two packet scheduling algorithms are studied and verified. Keywords—general-purpose many-core; network processor; verification platform; packet scheduling algorithm; FPGA
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