Verilog Code Generation Scheme from Signal Language

Abstract

Signal is a high-level declarative data flow language and has been successfully used for the design and implementation of reactive safety-critical embedded systems. The verified automatic code can be generated for various languages (C, C++, and Java) from the open source Signal framework (Polychrony Toolset). However, open source tool for automatic code generation from Signal language to Hardware Description Languages (HDLs) is not available. In this paper, we present a methodology of code generation from Signal language to Verilog. Verilog code is generated from the transformed Signal program based on guard's hierarchy and their associated sub-graph. Hardware structure is by default concurrent in nature; therefore, it is well-suited to generate code from Signal to HDL. It will provide more options for the designer when some part or complete application is required to be implemented in hardware.