Abstract
Due to the ever increasing complexity of embedded and cyber-physical systems, corresponding design solutions relying on modelling languages such as Unified Modelling Language (UML)/Object Constraint Language (OCL) find increasing attention. Due to the recent success of formal verification techniques, UML/OCL models also allow to verify and/or check certain properties of a given model in early stages of the design phase. To this end, different approaches for verification and validation have been proposed. In this work, the authors motivate, define, and describe different verification tasks for structural, as well as behavioural UML/OCL models that can be solved using solvers for Boolean satisfiability. They describe how these verification tasks can be translated into a symbolic formulation which is passed to off-the-shelf solvers afterwards. The obtained results enable designers to draw conclusions about the correctness of the considered model.
Highlights
The design of today’s computing devices is one of the most complex problems Electronic Design Automation (EDA) is currently facing
While the design evolved from the Register Transfer Level to the Electronic System Level in the past, new trends include the exploitation of modelling languages such as the Unified Modelling Language (UML [1]) and the Object Constraint Language (OCL [2])
At the same time, ensuring the correctness of a system is going to become a crucial bottleneck in today’s design flows. Since modelling languages such as UML/OCL allow for formal descriptions, they enable designers to verify whether the model of a system is correct or not
Summary
The design of today’s computing devices (including embedded and cyber-physical systems) is one of the most complex problems Electronic Design Automation (EDA) is currently facing. At the same time, ensuring the correctness of a system is going to become a crucial bottleneck in today’s design flows Since modelling languages such as UML/OCL allow for formal descriptions, they enable designers to verify whether the model of a system is correct or not. A promising approach to conduct corresponding verifications is to translate the models and the corresponding verification tasks into an instance of a language that can be processed by a formal verification tool. Translating UML/OCL [1, 2] models to Alloy first and to SAT in order to utilise formal verification is easier than directly translating it to SAT It is not surprising, that the overhead generated by the additional transformation yields worse results, i.e. worse performance, compared with the direct translation [6, 7].
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