Verifying Linear Real-Time Logic Specifications

Abstract

Formal specification and verification are critical to the development of safe real-time and embedded systems, which have become increasingly complex. Real-time logic (RTL) has been used to describe the specification and safety assertion of real-time systems. However, the satisfiability problem for RTL, as well as other first-order logics, is undecidable. There exist already non-trivial fragments of RTL, like path RTL and extended path RTL, for which the verification can be done efficiently. The key idea used by these RTL fragments was the so-called constraint graph. The constraint graph can express dependencies between two events, but cannot describe dependencies between three or more events. This paper presents a larger class than existing fragments of RTL for which the verification problem can also be solved efficiently. Our new class is called linear real-time logic (LRTL) and includes the existing decidable RTL fragments like path RTL and extended path RTL. The LRTL class is able to express any linear timing constraint with an arbitrary number of events variables (e.g., between three or more events). The main ingredient of the LRTL class is the use of matrices instead of the constraint graph, as a more powerful data structure capable of performing the conversion from RTL to a prepositional formula. The unsatisfiability of the prepositional formula will ensure the safety and feasibility of the given real-time system. Experimental results show that the execution times for LRTL are better than the systems expressed in extended path RTL, and comparable with those expressed in path RTL.