Verifying Complex Interaction between Hardware Processes

Ramineni Ramineni

doi:10.3844/jcssp.2009.154.162

Abstract

Problem statement: Verification of correct functionality of semiconductor devices has been a challenging problem. Given the device fabrication cost, it is critical to verify the expected functionality using simulations of executable device models before a device manufactured. However, typical industrial scale devices today involve large number of interactions between their components. Complexity of verifying all interactions becomes almost intractable even in simulation. The infeasible interactions need to be eliminated from verification consideration in order to reduce the complexity of the problem. Also an empirical metric of completeness of the verification of such interactions is needed. This metric should provide measure of quality of verification as well as that of degree of confidence in future correct behavior of the device. Metric should guide stimulus generation for simulation so that all aspects of the device functionality can be covered in verification. Existing coverage metrics focus almost exclusively on verification of individual components. Approach: In this study, interactions between device components modeled as independent processes, were considered. The interactions considered between control flow paths in different processes. Present algorithm analyzed the dependency between the control flow paths. It was also determined set of feasible interactions between the control flow paths and pruned out the infeasible ones. Remaining set of feasible interactions constituted our interaction coverage metric. Our metric handled device designs with an arbitrary number of processes. Results: Number of interactions to be considered in simulation-based verification was significantly reduced by our coverage metric using our proposed algorithms. This limited the complexity and scope of stimulus generation to coverage of only set of feasible interactions. Conclusion: Proposed coverage metric was able to provide realistic measure of degree of verification of components interactions as well as effectively guide the test generation process for device designs consisting of an arbitrary number of components.

Highlights

The advances in the manufacturing process technologies over the past two decades have made it possible to produce extremely complex semiconductor devices
We present a coverage metric, which evaluates the extent of verification of the interactions between processes
We model the behavior of each process as a Control-Flow Graph (CFG) and assume that executing all control-flow paths in a single process is sufficient to validate that process

Summary

Introduction

The advances in the manufacturing process technologies over the past two decades have made it possible to produce extremely complex semiconductor devices. The ability to design such devices and verify their correct behavior still lags the advances in the process technologies. The device model would be considered verified and the design sent out for manufacturing. This problem becomes even more pronounced when devices with numerous interacting components need to be verified for their correctness before signoff to the expensive manufacturing processes. These interacting components are modeled in the simulation model as concurrently executing independent processes. The second step is the testing of the interactions between the individual functional units and this is the problem addressed in this study. A notion of completeness is required to measure the extent to which such interactions are covered in simulations

Methods

Results

Discussion

Conclusion