Verification of physical designs using an integrated reverse engineering flow for nanoscale technologies

Abstract

Considering the potential risks of piracy and malicious manipulation of complex integrated circuits using worldwide distributed manufacturing sites, an effective and efficient reverse engineering process allows the verification of the physical layout against the reference design. This paper provides an overview of the current process and details on a new tool for the acquisition and synthesis of large area images and the recovery of the design from a physical device. Using this reverse engineering process on a physical chip layout, a circuit graph based partitioning of circuit blocks and an Elliptic Curve Cryptography (ECC) module identification will be performed. For the first time, the error between the generated layout and the design GDS layout will be compared quantitatively as a figure of merit (FoM). We propose a new classification of malicious manipulations based on their layout impact.