Verification of FPGA Layout Generators in Higher-Order Logic

Abstract

Manual placement of components is often used in FPGA circuit design in order to achieve better results than would be generated by automatic place and route algorithms. However, explicit placement of basic elements in parametrized hardware descriptions is tedious and error-prone. We describe a framework for the description and verification of parametrized hardware libraries with layout information, supporting both placing components with explicit symbolic coordinates and `neighboring' placement directives such as A beside B. The correctness of generated layouts is established by proof in higher-order logic, automated by using the Isabelle theorem prover. We have developed an extensive library of theorems describing properties of layouts that are combined by our compiler and the theorem prover to achieve a high level of automation in the verification of complete circuit layouts, making formal verification of circuit layouts practical with minimal user effort. Our system has been used to verify layout descriptions for a range of circuits that have been mapped to Xilinx FPGAs.