Verification of communication based SoC using advanced verification methodology

Abstract

Now a days verification has become one of the most important challenges in getting advanced SOC devices in the market. With the advancement of technology, there is a need to integrate more components in SoC that results in increased chip complexity. This complexity issue in SoC must be resolved by some advanced methodology. Industry experts consider that in the overall design effort, the verification effort is almost 70% to 80%. To increase the verification productivity, along with verification language, a proper methodology must be used to facilitate reuse to maximum extent under different design IP configurations. This advanced reusable test bench development increases the availability of a chip in the market. It is helpful in using the same code in sub-block, block and top level as well. This test bench development using advanced verification methodology helps in reducing cost and decreases the time to market for the chip.