VERIFICATION OF AUTOMATONS BY MODEL CHECKING METHOD

Abstract

The article analyzes software verification of control systems based on finite state machines, presents a classification of software correctness checks, advantages and disadvantages of various approaches to software verification, and, as a result, justifies the use of static verification methods, namely the model checking method. To solve applied problems, it is proposed to use the NuSMV software verifier. A brief overview of NuSMV verifier is given. The route of verification of software written in automaton style by the method of model checking is described. Each stage is described in the example of two interacting automata method. The construction of the model is described from a verbal description of its transformation into a finite state machine model with intermediate states and the transformation of the automaton into a formal finite state machine model in the SMV language, which is the input data for the NuSMV verifier. A description of the requirements for the model is presented, ranging from a verbal description of the requirements to the formalization of requirements in language of the temporal logic CTL. Based on the obtained model in SMV language and the obtained formalization of the requirements in CTL temporal logic language, NuSMV verifier checks the feasibility of the obtained requirements on the obtained model of the automata system. An analysis of the results of verification according to the specified requirements is given. For verification, an error was introduced into the model, leading to a negative result of the feasibility of the specified requirements. The verifier indicated the presence of an error and the path leading to it. Based on the results of the analysis of the results, a conclusion is made about the need to use this verification method in tasks of responsible applications. Further steps for the development and implementation of this method are described.