Verification Method of Safety Properties of Embedded Assembly Program by Combining SMT-Based Bounded Model Checking and Reduction of Interrupt Handler Executions

Satoshi Yamane,Junpei Kobashi,Kosuke Uemura

doi:10.3390/electronics9071060

Abstract

Embedded software has properties dependent on hardware (direct operation of address spaces, memory mapped I/O, interruption, etc.). Therefore, demands about the established method of formal verifications corresponding to those properties are increasing from the point of view of shorter development and high reliability. Our study aims at enabling a formal verification with Satisfiability Modulo Theories-Based Bounded Model Checking (SMT-Based BMC) of safety for embedded assembly codes. Our proposed method generates models of assembly codes in detail with the fixed-sized bit-vectors theory. The models generated by our method include interrupts, and the size of the models is reduced using Interrupt Handler Execution Reduction (IHER) technique. In this paper, we have developed the verification method of safety properties of embedded assembly program by combining SMT-Based Bounded Model Checking and Reduction of Interrupt Handler Executions. Moreover, we show the evaluation of our method by experiments using prototype model checker.

Highlights

In order to reduce the number of blocks, we propose the method of making the block of codes, at which interruptions do not occur
We model registers and values of assembly codes using Fixed-Size Bit-Vector theory, and construct a transition system
We reduce the number of Interrupt Handler (IH) executions by blocking IHs at program locations using Interrupt Handler Execution Reduction (IHER), and make a set of basic blocks from assembly codes blocking IHs

Summary

Introduction

Testing is not sufficient for embedded systems as there are errors that are difficult to find by testing. There are standards such as IEC61508 [3] that recommend the application of formal methods such as formal verification methods. SMT solvers enable SMT-Based Bounded Model Checking over infinite domains. Program Verification by SMT-Based Bounded Model Checking. B. Schlich et al have developed an abstraction technique called IHER, which reduces the number of IH executions by blocking IHs at program locations where there is no dependency between certain. By the same method as partitioning program codes into basic blocks [6,7], we partition assembly codes into blocks. The blocks become the nodes of CFG, whose edges indicate which blocks can follow which other blocks

Methods

Results

Conclusion