Varying Resolution Pipelined ADC for Direct IF Sampling Receiver in Wireless Sensor Networks

Abstract

Cheap and efficient sensor nodes aid in the development of the technology needed for IoT and wireless sensor networks. A critical component in these systems is the RF transceiver and it has been shown that lowering the power of the ADC significantly reduces the overall power consumption of wireless sensor nodes. This work presents a pipelined ADC with adaptive resolution based on the received signal for an IF-sampling receiver to reduce the power consumption of a wireless sensor node. Based on the modeling of a low-power wide-area network (LPWAN) transceiver with an output SNR of −3dB, the ADC needed only 6, 8, and 10 bits of resolution to properly decode a message signal, whose amplitude varies with a distance of 1–15 km based on propagation loss assuming constant transmit power. The pipelined ADC was composed of 10 different stages which were turned on or off based on the resolution needed, as determined by the detected amplitude of the message signal. Stages 1–2 and stages 1–4 were turned off for 8-bit and 6-bit configurations, respectively. The pipelined ADC was designed using a 65nm CMOS process with 1V supply and the power consumption of the 10, 8, and 6 bit states were 23mW, 16.5mW, and 13mW, respectively, with a 1Vpp differential full-scale voltage for all configurations. The static performance of the ADC was tested in the schematic level using a 600mVpp slow ramp and achieved an INL of within 0.875, 0.25, and 0.125 LSB for 10, 8, and 6 bit configurations, respectively. Dynamic tests were also done using a 600mVpp 10MHz sinusoidal input and an ENOB of 9.3, 7.9, and 5.8 bits were achieved for 10, 8, and 6 bit configurations, respectively.