Variation-Tolerant Write Completion Circuit for Variable-Energy Write STT-RAM Architecture

Abstract

In this paper, we demonstrate an energy-reduction strategy that overcomes the stochastic switching characteristics of the spin-torque-transfer magnetic-RAM (STT-RAM) write operation and propose a write completion circuit needed for it. In contrast to the traditional worst case approach, which fixes the write duration for all cells, the proposed write technique terminates the write pulse after a write process finishes by monitoring the state of a cell. Since the average write duration is far shorter than the worst case duration, the average write energy is significantly reduced by the proposed architecture. We developed a write completion circuit for state change detection and bitline termination, and evaluated it using a compact STT-RAM model targeting an implementation in a 16-nm technology node. We also developed a variation-tolerant version of the design specifically suited for handling significant variation in process parameters for both FETs and magnetic tunnel junctions (MTJs), and the low value of tunnel magnetoresistance of practical MTJs. Analysis indicates that at the required write-error rate, the proposed architecture reduces write energy by 36%-97% compared with the conventional designs relying on the worst case approach.